1. Technical Field
The present invention relates to a voltage regulator, and more particularly, to a voltage regulator with improved voltage regulator response and reduced voltage drop.
2. Background
Linear voltage regulator integrated circuits are widely used in electronic systems, particularly in applications which require power supplies with low noise and low ripple. In a DRAM (Dynamic Random Access Memory), LDO regulators supply power to the array peripheral such as data path, pumps to other noise-sensitive analog circuit blocks.
In a traditional voltage regulator, response time and voltage drop affect the performance of the voltage regulator. A faster response time can regulate voltage more quickly, while a lower voltage drop can reduce the ripple of the output voltage. Extra feedback resistors and feedback capacitors improve device performance. However, in a low power device, the voltage regulator needs to enter the power down mode in order to save power. Switching between an enable mode and a non-enable mode is important for the voltage regulator. The previous design, which attempted to improve the response time and voltage drop of the voltage regulator, required extra power dissipation and large layout size. Extra resistors and capacitors will increase the layout area. In addition, the resistors and capacitors require different settings for the enable mode and the non-enable mode. To address the above-mentioned shortcomings, the traditional voltage regulator design needs an improvement for feedback compensation.
In a DRAM device, voltage regulators are traditionally turned off during periods of low current demand such as power down and bank idle, and are turned on during active read/write. During power down, when there is no current demand, almost all the voltage regulators are turned off except a standby voltage regulator, which has slow response because of the small bias current to save power. However, when moving out of the power down mode, a large current demand appears, and all the voltage regulators are turned on in response to the large current load. With the process scaling down, the DRAM transfers from DDR to DDR2 and DDR3 and the supply voltage reduces from 2.5V to 1.5V, even 1.35V, then the voltage regulator response reduces linearity with the supply voltage change The result is significantly reduced frequency response and switching speed of the CMOS amplifier. Therefore, there is a need to improve the time response of the present voltage regulator.